6
FN4640.5
November 18, 2004
Adjusting the Fault Reporting and Power
Supply Latch-Off Delay Times
Figure 5 illustrates the relationship between the FLTN signal
and the gate drive outputs. Duration a, indicates the time
between FLTN starting to transition from High to Low,
(indicating a fault has occurred) and the start of the gate
drive outputs latching off. The latch-off is initiated by the
falling FLTN signal reaching the output latch threshold
voltage, VFLTN, TH. For additional details and wave forms
see HIP1011A Data Sheet FN4631. Table 1 illustrates the
effect of the FLTN capacitor on the response times.
Typical Performance Curves
FIGURE 1. r
ON
vs TEMPERATURE
FIGURE 2. OC VTH vs TEMPERATURE (VR
OCSET
= 1.21V)
FIGURE 3. OCSET CURRENT vs TEMPERATURE
FIGURE 4. V
CC
POWER ON RESET VTH vs TEMPERATURE
340
320
300
280
260
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70
1000
900
800
700
600
TEMPERATURE (
o
C)
PMOS +12 r
ON
NMOS -12 r
ON
105
95
85
75
65
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70
TEMPERATURE (
o
C)
5V OCVTH
3V OCVTH
102
101
100
99
98
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70
TEMPERATURE (
o
C)
9.5
9.4
9.3
9.2
9.1
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70
TEMPERATURE (
o
C)
TABLE 1. RESPONSE TIME TABLE
0.001?/SPAN>F
0.1?/SPAN>F
10?/SPAN>F
3V5VG Response a
0.85祍
37祍
3.8ms
FIGURE 5. TIMING DIAGRAM
3V5VG
FLTN
a
T1
T2
V
FLTN,TH
HIP1011B